1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and in particular to a so-called flash memory, i.e., an EEPROM (electrically Erasable and Programmable Read Only Memory) allowing electrical erasing and writing of information, and a method of manufacturing the same.
2. Description of the Background Art
EEPROMs have been known as a kind of nonvolatile semiconductor memory devices which allow free programming of data and also allow electrical writing and erasing of information. Although the EEPROM has an advantage that both writing and erasing can be executed electrically, it requires two transistors, i.e., a select transistor and a memory transistor for each memory cell, so that integration to a higher degree is difficult. In view of this, there has been proposed a flash EEPROM, in which each memory cell is formed of one transistor, and entire written information charges can be electrically erased at a time. This is disclosed, for example, in U.S. Pat. No. 4,868,619.
FIG. 81 is a block diagram showing a general structure of a flash memory. Referring to FIG. 81, the structure includes a memory cell matrix 100, an X-address decoder 200, a Y-gate 300, a Y-address decoder 400, an address buffer 500, a write circuit 600, a sense amplifier 700, an I/O buffer 800 and a control logic 900.
Memory cell matrix 100 includes a plurality of memory transistors arranged in a matrix form. Memory matrix 100 is connected to X-address decoder 200 and Y-gate 300. X-address decoder 200 and Y-gate 300 function to select rows and columns in memory cell matrix 100, respectively. Y-gate 300 is connected to Y-address decoder 400. Y-address decoder 400 functions to provide information for selecting columns. X-address decoder 200 and Y-address decoder 400 are connected to address buffer 500. Address buffer 500 functions to store temporarily address information.
Y-gate 300 is connected to write circuit 600 and sense amplifier 700. Write circuit 600 functions to perform writing during data inputting. Sense amplifier 700 functions to determine "0" or "1" as a value of a current which flows during data outputting. Write circuit 600 and sense amplifier 700 each are connected to I/O buffer 800. I/O buffer 800 functions to store temporarily input/output data.
Address buffer 500 and I/O buffer 800 are connected to control logic 900. Control logic 900 functions to control the operation of flash memory. Control logic 900 performs control based on a chip enable signal /CE, an output enable signal /OE and a program signal. Characters "/" in reference characters such as "/CE" mean inversion.
FIG. 82 is an equivalent circuit diagram showing a schematic structure of memory cell matrix 100 shown in FIG. 81. Referring to FIG. 82, memory cell matrix 100 is provided with a plurality of word lines WL.sub.1, WL.sub.2 . . . , WL.sub.i and a plurality of bit lines BL.sub.1, BL.sub.2 . . . , BL.sub.j which extends perpendicularly to each other to form a matrix. The plurality of word lines WL.sub.1 WL.sub.2 . . . , WL.sub.i are connected to X-address decoder 200 and are disposed in the row direction. The plurality of bit lines BL.sub.1 BL.sub.2 . . . , BL.sub.j are connected to Y-gate 300 and are disposed in the column direction.
Memory transistors Q.sub.11, Q.sub.12, . . . , Q.sub.ij are arranged at crossings of the word lines and bit lines, respectively. Each memory transistor has a drain connected to the corresponding bit line. A control gate of each memory transistor is connected to the corresponding word line. A source of each memory transistor is connected to the corresponding source line S.sub.1, S.sub.2 . . . , S.sub.i. The sources of memory transistors belonging to the same row are mutually connected.
A structure of each memory transistor forming the conventional flash memory will now be described below.
FIG. 83 is a fragmentary plan showing a schematic structure of memory cell matrix 100 of the conventional flash memory. FIG. 84 is a cross section taken along line D-D' in FIG. 83.
Referring mainly to FIG. 84, a p-type silicon substrate 1 is provided at its main surface with drain diffusion regions 13 and a source diffusion region 12 which are spaced from each other with channel regions 2 therebetween, respectively. A floating gate electrode 4 is formed on each channel region 2 with a thin oxide film 3 of about 100 .ANG. in thickness therebetween. A control gate electrode 6 is formed on floating gate electrode 4 with an interlayer insulating film 5 therebetween. Floating gate electrode 4 and control gate electrode 6 are made of polycrystalline silicon doped with impurity, which will be referred to as "doped polycrystalline silicon" hereinafter. A thermal oxide film 51 is formed over p-type silicon substrate 1, floating gate electrode 4 and control gate electrode 6. A smooth coat film 8 made of, e.g., an oxide film is formed over floating gate electrode 4 and control gate electrode 6.
Smooth coat film 8 is provided with a contact hole 9 reaching a portion of a surface of source diffusion region 12. A bit line 52, which has a portion electrically connected to source diffusion region 12 through contact hole 9, extends on smooth coat film 8.
Referring mainly to FIG. 83, the plurality of word lines 6 are arranged perpendicularly to the plurality of bit lines 52. Each word line 6 is integral with the plurality of control gate electrodes 6. At each of crossings of word lines 6 and bit lines 52, there is formed floating gate electrode 4 located under control gate electrode 6. There are also formed element isolating oxide films 53, each of which is formed between two areas each including two floating gate electrodes 4 neighboring to each other in the column direction.
Referring to FIG. 85, description will be given on a write operation of a flash EEPROM utilizing channel hot electrons. A voltage V.sub.D1 of about 6 to 8V is applied to drain diffusion region 13, and a voltage V.sub.G1 of about 10 to 15V is applied to control gate electrode 6. Voltages V.sub.D1 and V.sub.G1 thus applied generate a large amount of high energy electrons near drain diffusion region 13 and oxide film 3. The electrons thus generated are partially introduced into floating gate electrode 4. Since the electrons are accumulated in floating gate electrode 4 in this manner, a threshold voltage V.sub.TH of the memory transistor increases. The state where threshold voltage V.sub.TH is higher than a predetermined value is a written state and is called a "0" state.
Referring to FIG. 86, an erase operation utilizing an F-N (Fowler-Nordheim) tunnel phenomenon will be described below. A voltage V.sub.S of about 10 to 12V is applied to source diffusion region 12, control gate electrode 6 is set to the ground potential, and drain diffusion region 13 is held at the floating state. Voltage V.sub.S applied to source diffusion region 12 generates an electric field, which causes the F-N tunnel phenomenon to move electrons from floating gate electrode 4 through thin oxide film 3. Since electrons are removed from floating gate electrode 4, threshold voltage V.sub.TH of the memory transistor lowers. The state where threshold voltage V.sub.TH is lower than the predetermined value is an erased state and is called an "1" state.
In a read operation, a voltage V.sub.G2 of about 5V is applied to control gate electrode 6 shown in FIG. 84, and a voltage V.sub.D2 of about 1 to 2V is applied to drain diffusion region 13. The foregoing determination of "1" or "0" is performed based on whether a current flows through the channel region of memory transistor, i.e., whether the memory transistor is on or off. Thereby, information is read.
For the flash memory described above, there has been proposed a drain structure (which will be referred to as a "pocket structure") shown in FIGS. 87 and 88 in order to improve write characteristics. FIG. 88 shows, on an enlarged scale, a region S in FIG. 87.
A structure shown in FIGS. 87 and 88 is provided with a p-type pocket region 15 which is in contact with drain diffusion region 13 and covers the periphery of the same. p-type pocket region 15 has an impurity concentration higher than that of the p-type silicon substrate. This raises an electric field at a drain end (region T in FIG. 88) in a pn junction (formed of drain diffusion region 13 and pocket region 15) as shown in FIG. 89.
FIG. 89 shows electric fields in a direction parallel to each channel along line F-F' in FIG. 88. More specifically, FIG. 89 shows at (a) the electric field in a structure not provided with the pocket region, and shows at (b) the electric field in a structure provided with the pocket region.
Provision of the pocket structure increases a rate of electrons having a high energy in all electrons running through the channel. This promotes introduction or injection of electrons into the gate, and thus increases the gate current.
As is apparent from the above, the pocket structure is employed for improving the write characteristics by increasing the absolute quantity of channel hot electrons.
By employing the pocket structure, the electric field (Ex) parallel to the channel can be enhanced at the drain end as described above, and a probability of generation of high energy electrons can be improved.
However, generated high energy electrons move toward the drain. In order to inject the high energy electrons into the floating gate electrode, therefore, it is necessary to change the moving direction so that the high energy electrons may be directed toward the floating gate electrode by elastic scattering. However, electrons are randomly directed by elastic collision with impurity 60 as shown in FIG. 90. Therefore, only a part of electrons have a moment in the floating gate electrode direction, i.e., moment directed toward the floating gate electrode.
Since the electric field along the gate electrode direction in a bulk is low at a region where channel hot electrons generate, the probability that high energy electrons have the moment in the gate electrode direction after elastic collision is disadvantageously low.
In the pocket structure (FIGS. 87 and 88) described above, the electric field (longitudinal electric field) in a vertical direction with respect to the channel of insulating film 3 increases at the drain end where the most high energy electrons are generated. It is defined that an arrival probability is a probability that generated high energy electrons arrive at the floating gate. In this case, the longitudinal electric field in insulating film 3 acts to reduce the arrival probability by the following reason.
First, under the application condition that drain voltage Vd is smaller than gate voltage Vg, the longitudinal electric field and the lateral electric field (i.e., electric field parallel to the channel) in the insulating film 3 are distributed at the drain end as shown in FIG. 91. Referring to FIG. 91, the most high energy electrons generate near a point where the lateral electric field attains the highest value. However, the nearly maximum longitudinal electric field also generates at the point where the maximum lateral electric field generates. As the longitudinal electric field is larger, more electrons are forced to return toward the substrate, resulting in lowering of the probability that high energy electrons are injected into the floating gate electrode.
In the pocket structure described above, a majority of channel hot electrons generate at the drain end. As shown in FIG. 91, however, the drain end is a region at which the longitudinal electric field increases, and in other words, is a region at which a large force generates to return the injected electrons in the floating gate electrode toward the substrate. Therefore, the pocket structure cannot be considered as the structure which allows the generated hot electrons to be injected efficiently into the floating gate electrode.
FIG. 92B shows change in potential distribution along the vertical direction (line E-E' in FIG. 92A) with respect to the channel at the drain end shown in FIG. 92A. Under the condition that drain voltage Vd is smaller than gate voltage Vg, a potential difference at the insulating film 3 increases as the longitudinal electric field at the insulating film 3 increases. Therefore, increase of the longitudinal electric field at the insulating film 3 results in increase in height of the potential barrier of insulating film 3 over which electrons must move, as shown in FIG. 93. The electrons must have energies of a magnitude which allows them to move over at least the barrier of insulating film 3 in order to allow injection of electrons into the floating gate electrode. Therefore, as the longitudinal electric field at insulating film 3 (i.e., height of the barrier of insulating film 3) increases, a rate of electrons having energies allowing movement over the barrier of insulating film 3 decreases, provided that the generated electrons always have the same high energy. It can be considered from the foregoing that the arrival probability is restricted to a low value in the pocket structure in which both of lateral and longitudinal electric fields increase at the drain end.
As described above, the conventional pocket structure suffers from a problem that the longitudinal electric field is high at the point where the maximum lateral electric field generates and the most hot electrons are produced, so that the generated high energy electrons cannot be injected into the floating gate electrode with a high probability.